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rt9116 ? ds9116-00 november 2016 www.richtek.com 1 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. pin configuration (top view) wqfn-28l 4x5 10w stereo class-d speaker driver amplifier general description the rt9116 is a 10w per channel, high efficiency class d stereo audio amplifier for driving bridge tied load (btl) speakers. the rt9116 can drive stereo speakers with load as low as 4 . its high efficiency eliminates the need for an extra heat sink when playing music. the gain of the amplifier can be controlled by gain select pins. the outputs are fully protected against shorts to gnd, pvcc, and output to output with an auto recovery feature and monitored output. the rt9116 is available in the wqfn-28l 4x5 package. features ? ? ? ? ? 8v to 17v input supply range ? ? ? ? ? ? ? ? ? ? 10w / ch for an 8 load, 13v supply at 10% thd +n ? ? ? ? ? ? ? ? ? ? 15w / ch for an 8 load, 16v supply at 10% thd +n ? ? ? ? ? ? ? ? ? ? 90% efficiency eliminates need for heat sink ? ? ? ? ? dc detect protection ? ? ? ? ? filter-less operation ? ? ? ? ? over-temperature protection (otp) with auto recovery option ? ? ? ? ? surface mount 28-lead wqfn package applications ? lcd-tv ? monitors ? home audio ? amusement equipment ? electronic music equipment marking information package type qw : wqfn-28l 4x5 (w-type) lead plating system g : green (halogen free and pb free) rt9116 0j=ym dnn 0j= : product code ymdnn : date code bstnl pvddr voutnr bstnr voutpr 29 pvss 1 2 3 4 5 6 7 8 14 9 10111213 23 28 27 26 25 24 22 21 20 19 18 17 16 15 voutpl voutnl pvddl inpr nc avss gvdd nc inpl innr innl plimit bstpl gain en sr_ctrl avcc nc bstpr gvdd2 avss nc avss
rt9116 2 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit note : when pin gain connect (a) 100k to pvcc, spk gain = 31db; (b) 1k to gnd, spk gain = 26db bstpl voutpl 0.22f 2.2nf bstnl voutnl 0.22f 2.2nf bstpr voutpr bstnr voutnr 1f 1f 1f pvddl pvss pvddr gvdd plimit gain inpl innl inpr 1f 100f 0.1f 100f 0.1f en sr_ctrl r/nc 150k 1f innr bead bead audio source pvcc pvcc 100k 100k 1k control system 0.1f 0.1f 0.22f 2.2nf 0.22f 2.2nf bead bead rt9116 29 (exposed pad) 1 2 3 4 5 14 23 28 26 25 24 22 21 20 19 18 17 16 15 0.1f 1f avcc avss pvcc 10 6, 9, 10 27 gvdd2 13
rt9116 3 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 inpl positive audio input for left channel. 2 innl negative audio input for left channel. 3 innr negative audio input for right channel. 4 inpr positive audio input for right channel. 5 gvdd high-side fet gate drive supply. 6, 9 , 10 avss analog ground. 7, 8, 11, 12 nc no internal connection. 13 gvdd2 reference voltage from gvdd. 14 bstpr bootstrap i/o for right channel, positive high-side mosfet. 15 voutpr class-d h-bridge positive output for right channel. 16 pvddr power supply input for right channel h-br idge. right channel and left channel power supply inputs are connected internally. 17 voutnr class-d h-bridge negative output for right channel. 18 bstnr bootstrap i/o for right channel, negative high-side mosfet. 19 bstnl bootstrap i/o for left channel, negative high-side mosfet. 20 voutnl class-d h-bridge negative output for left channel. 21 pvddl power supply input for left channel h-bridge. right channel and left channel power supply inputs are connected internally. 22 voutpl class-d h-bridge positive output for left channel. 23 bstpl bootstrap i/o for left channel, positive high-side mosfet. 24 gain gain select least significant bit. 25 plimit power limit level adjustment. 26 sr_ctrl control output stage driver slew rate 27 avcc analog supply input. 28 en chip enable (active high). 29 (exposed pad) pvss power ground for power stage
rt9116 4 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional block diagram pwm generator pwm generator uvp ocp otp ovp inpl innl inpr outpl outnl outpr outnr bstpl bstnl bstpr bstnr pvddl pvddr gain plimit avcc avss reference voltage/current generator control logic en gvdd pvss sr_ctrl innr + - + - gvdd2 operation the rt9116 is a dual-channel 2 x 10w efficient, class d audio power amplifier for driving bridge-tied stereo speakers. the rt9116 uses the three-level modulation (bd model) scheme that allows operation without external lc reconstruction when the amplifier is driving an inductive load. moreover, the built-in spread spectrum modulation can efficiently reduce emi and save the cost of the external inductor, replaced by ferrite beads. a closed-loop modulator, which enables negative error feedback, can improve thd+n and psrr of output signals. the rt9116 offers two selectable power limit thresholds, 5w/10w under 8 for protecting load speakers. these two limit thresholds can be set easily by connecting two different resistors, 25k /150k , from the plimit pin to ground. though there is no requirement for power limit, the resistance connected from the plimit pin to ground must be greater than 500k . the rt9116 features over-current protection against output stage short-circuit conditions. when a short-circuit condition occurs, amplifier outputs will be switched to a hi-z state, and the short-circuit protection latch will be triggered. once the short-circuit condition is removed, the rt9116 will be automatically recovered. the rt9116 can drive stereo speakers as low as 4 . the high efficiency of the rt9116, 90%, eliminates the need for an external heat sink when playing music.
rt9116 5 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (pvddx = 12v, r l = 8 , t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) ? supply voltage, pvddl, pv ddr, avcc ----------------------------------------------------------------- ? 0.3v to 21v ? input voltage, en, gain -------------------------------------------------------------------------------------- ? 0.3v to (pvddx + 0.3v) ? output voltage, outpl,outpr,outnl,outnr ------------------------------------------------------- ? 0.3v to (pvddx + 0.3v) ? bootstrap voltage, bstpl,bstpr,bstnl,bst nr ---------------------------------------------------- ? 0.3v to (pvddx + 6v) ? other pins -------------------------------------------------------------------------------------------------------- ? 0.3v to (gvdd + 0.3v) ? power dissipation, p d @ t a = 25 c wqfn-28l 4x5 ------------------------------------------------------------------------------------------------- 3.64w ? package thermal resistance (note 2) wqfn-28l 4x5, ja -------------------------------------------------------------------------------------------- 27.4 c/w wqfn-28l 4x5, jc ------------------------------------------------------------------------------------------- 2 c/w ? lead temperature (soldering, 10 sec.) -------------------------------------------------------------------- 260 c ? junction temperature ------------------------------------------------------------------------------------------ 150 c ? storage temperature range --------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) ? supply input voltage, pvddl, pvddr, avcc ---------------------------------------------------------- 8v to 17v ? min. spk load in btl mode, rspk (btl) ---------------------------------------------------------------- 4 ? junction temperature range --------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range --------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test condition min typ max unit gate drive supply voltage v gvdd i gvdd = 2ma -- 5 5.5 v en, gain input voltage v ih : high-level v ih 3 -- -- v v il : low-level v il -- -- 0.8 v en, gain input current v ih : high-level i ih en, gain, vi = 5v -- -- 50 ? a v il : low-level i il en, gain, vi = 0.8v -- -- 10 ? a output offset voltage vos pvddx = 12v, gain = 31db -- -- 20 mv quiescent current i q pvddx = 12v, gvdd2 = 5v, no filter and load -- 10 15 ma shutdown current i sd pvddx = 12v, gvdd2 = 5v, en = low -- 1 1.5 ma drain-source on state resistance r ds(on) pvddx = 12v, i o = 500ma high-side -- 250 -- m ? low-side -- 200 -- gain gain gain = 0 25 26 27 db gain = 1 30 31 32
rt9116 6 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured under natural convection (still air) at t a = 25 c with the component mounted on a high effective- thermal-conductivity four-layer test board on a jedec 51-7 thermal measurement standard. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test condition min typ max unit output integrated noise vn pvddx = 12v, gain = 26db, a-weighted -- 100 -- ? v pvddx = 12v, gain = 31db, a-weighted -- 200 -- signal-to-noise ratio snr pvcc = 12v, gain = 26db, a-weighted, thd+n = 1% -- 98 -- db output power po thd+n = 7%, pvcc = 11.3v, r l = 8 ? -- 8 -- w thd+n = 10%, pvcc = 16v, r l = 8 ? -- 15 -- w total harmonic distortion plus noise thd+n pvddx = 12v, fin = 1khz po = 5w -- 0.2 -- % po = 1w -- 0.1 -- crosstalk vo = 1vrms, gain = 26db, fin = 1khz -- ? 70 -- db power supply ripple rejection psrr 200mvpp ripple at 1khz, gain = 26db, inputs ac-coupled to agnd -- ? 70 -- db turn on time t on -- 25 -- ms turn off time t off -- 2 -- ? s oscillator frequency f osc -- 330 -- khz output power limit v in 1vrms, plimit , 25k ? to gnd 5 -- 6.5 w v in = 1vrms, plimit , 150k ?? to gnd 10 -- 13 protection circuitry under-voltage protection v uvp -- 6.5 -- v under-voltage protection hysteresis ? v uvp -- 1 -- v over-voltage protection v ovp -- 19 -- v over-voltage protection hysteresis ? v ovp -- 2 -- v over-temperature protection t sd -- 170 -- ? c over-temperature protection hysteresis ? t sd -- 15 -- ? c spk over-current protection i ocp -- 3.5 -- a
rt9116 7 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output power vs. supply voltage 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 supply voltage (v) output power (w) efficiency vs. output power 0 10 20 30 40 50 60 70 80 90 100 012345678910 output power (w) efficiency (%) typical operating characteristics pvcc = 12v, f = 1khz, gain = 26db r l = 8 r l = 6 r l = 4 output power (w) thd+n vs. output power 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 pvcc = 12v, r l = 8 , gain = 26db thd+n (%) 10m 20m 50m 100m 200m 500m 1 2 5 10 20 frequency (hz) thd+n vs. frequency 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.006 pvcc = 12v, r l = 8 , gain = 26db thd+n (%) 20 50 100 200 500 1k 2k 5k 10k 20k 1khz 20hz 10khz 0.5w 2.5w 5w frequency (hz) crosstalk vs. frequency 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 pvcc = 12v, r l = 8 , gain = 26db, po = 1w crosstalk (db) 20 50 100 200 500 1k 2k 5k 10k 20k r to l l to r frequency (hz) frequency results 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 pvcc = 12v, r l = 8 , gain = 26db, po = 1w dbv (db) 20 50 100 200 500 1k 2k 5k 10k 20k thd+n = 10% thd+n = 1% r l = 8 , gain = 26db, stereo out
rt9116 8 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information gvdd supply the gvdd is used to supply the gate drivers for the output full bridge transistors. connect a 1 f capacitor from this pin to ground for good bypass. the typical gvdd output voltage is 5v. amplifier gain setting the gain of the rt9116 amplifier can be set by one input terminals, gain shown as table 1. the gain setting is realized by changing the taps on the input resistors and feedback resistors inside the amplifier. this causes the input impedance (zi) to be dependent on the gain setting. the actual gain settings are controlled by the ratios of the resistors, so the gain variation from part-to-part is small. however, the input impedance from part-to-part at the same gain may shift by 20% due to shifts in the actual resistance of the input resistors. gain amplifier gain (db) input impedance (k ? ) typ typ 0 26 20 1 31 10 table 1. gain setting en operation the rt9116 employs a shutdown mode operation designed to reduce supply current (icc) to the absolute minimum level for power saving. the en input terminal should be held high (see specification table for trip point) in normal operation. pulling en low causes the outputs to mute and the amplifier to enter a low current state. leaving en floating will cause the amplifier operation to be unpredictable. never leave en pin unconnected. for the best power-off pop performance, turn off the amplifier in the shutdown mode prior to removing the power supply voltage. over-current protection (ocp) the rt9116 provides ocp function to prevent the device from damages during overload or short-circuit conditions. the current are detected by an internal sensing circuit. once overload happens, the ocp function is designed to operate in auto-recovery mode. dc detect protection rt9116 has circuitry which will protect the speakers from dc current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. to clear the dc dete ct it is necessary to cycle the pvcc supply. adc detect fault is issued when the output differential duty-cycle of either channel exceeds 18% (for example, +59%, ? 41%) for more than 290 msec at the same polarity. this feature protects the speaker from large dc currents or ac currents less than 4hz. to avoid nuisance faults due to the dc detect circuit, hold the sd pin low at power- up until the signals at the inputs are stable. also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance dc detect faults. under-voltage protection (uvp) the rt9116 monitors the voltage on pvdd voltage threshold. when the voltage on pvddl and pvddr pin falls below the under voltage threshold, 7v (typ.), the uvp circuit turns off the output immediately and operates in cycle by cycle auto-recovery mode. over-voltage protection (ovp) the rt9116 monitors the voltage on pvdd voltage threshold. when the voltage on pvddl and pvddr pin rise behind the over voltage threshold, 15v (typ.), the ovp circuit turns off the output immediately and operates in cycle by cycle auto-recovery mode. over-temperature protection (otp) the otp prevents damage to the device when the internal die temperature exceeds 170 c. there is a 15 c tolerance on this trip point from device to device. once the die temperature exceeds the otp threshold, the device enters
rt9116 9 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. into the shutdown state and the outputs are disabled. this is not a latched fault. the thermal fault is cleared once the temperature of the die is reduced by 15 c. the device begins normal operation at this point with no external system interaction. power-on/off sequence use the following sequence to power on the device ?? pvcc power supply ready. past en = 1 (en pin goes high) figure 1. power on sequence figure 2. power off sequence use the following sequence to power off the device ? en = 0 (en pin goes low) past pvcc power supply shutdown thermal considerations the junction temperature should never exceed the absolute maximum junction temperature t j(max) , listed under absolute maximum ratings, to avoid permanent damage to the device. the maximum allowable power dissipation depends on the thermal resistance of the ic package, the pcb layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. the maximum power dissipation can be calculated using the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction-to-ambient thermal resistance. for continuous operation, the maximum operating junction temperature indicated under recommended operating conditions is 125 c. the junction-to-ambient thermal resistance, ja , is highly package dependent. for a wqfn-28l 4x5 package, the thermal resistance, ja , is 27.4 c/w on a standard jedec 51-7 high effective-thermal- conductivity four-layer test board. the maximum power dissipation at t a = 25 c can be calculated as below : p d(max) = (125 c ? 25 c) / (27.4 c/w) = 3.64w for a wqfn-28l 4x5 package. the maximum power dissipation depends on the operating ambient temperature for the fixed t j(max) and the thermal resistance, ja . the derating curves in figur e 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. power limit the voltage at the plimit pin can used to limit the power to levels below that which is possible based on the supply rail. add a resistor (table 2) to ground set the voltage at the plimit pin. also add a 1 f capacitor from the plimit pin to ground. the plimit circuit sets a limit on the output power. resistor (k ? ) output power (w) 25 5.75 150 11.5 open max table 2. plimit setting pvcc en pvcc en figure 3. derating curve of maximum power dissipation 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
rt9116 10 ds9116-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 4. pcb layout guide layout considerations for the best performance of the rt9116, the below pcb layout guidelines must be strictly followed. place the decoupling capacitors as close as possible to the avcc, pvddl, pvddr and gnd pins. for achieving a good quality, consider adding a small, good performance low esr ceramic capacitor between 220pf and 1000pf and a larger mid-frequency capacitor between 0.1 f and 1 f to the pvdd pins of the chip. the traces of (linp & linn, rinp & rinn) and (outpl & outnl, outpr & outnr) should be kept equal width and length respectively. the thermal pad must be soldered to the pcb for proper thermal performance and optimal reliability. the dimensions of the thermal pad and thermal land should be larger for application. the vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the pcb. gnd gnd gnd pvdd en avcc sr_ctrl plimit gain bstpl avss avss nc nc gvdd2 bstpr inpl innl innr inpr gvdd avss nc nc voutpl pvddl voutnl bstnl bstnr voutnr pvddr voutpr gnd pvdd gnd pvdd en sr_ctrl plimit gain the decoupling capacitor (cs) must be placed as close to the ic as possible the decoupling capacitor (cs) must be placed as close to the ic as possible the decoupling capacitor (cs) must be placed as close to the ic as possible c b c b c in c in c in c in the gate driver output decoupling capacitor (cg) must be placed as close to the ic as possible audio input fb fb fb fb c b c b cg gnd pvss (thermal pad) tied to gnd
rt9116 11 ds9116-00 november 2016 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension symbol dimensions in millimeters dimensions in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.900 4.100 0.154 0.161 d2 2.600 2.700 0.102 0.106 e 4.900 5.100 0.193 0.201 e2 3.600 3.700 0.142 0.146 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 28l qfn 4x5 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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